In the field of power integrated circuits a host of unique problems confront designers. One such problem is nonuniform current distribution in bus routing, leading to potential reliability problems due to electromigration and resulting in poor safe operating area performance (hereafter referred to as SOA). Nonuniform current distribution can be caused by metal thinning, metal voiding or poor step coverage along the bus. These may create hot spots (regions of simultaneous high voltage and high current) on the semiconductor die which in turn can create potential reliability problems when operating semiconductor devices at high power levels.
Another primary area of concern is die area. As designers strive to design higher performance circuits at lower cost the busing used to carry current to and from power transistors becomes a primary factor. Large current quantities require wide buses to meet the current density specifications. These buses require a significant amount of die area with the problem becoming compounded with devices having multiple conducting regions, multiple surface electrodes, or a combination of both multiple conducting regions and multiple electrodes on the surface.
It is an object, therefore, of this invention to provide an improved bus structure for a power integrated circuit device.
Other objects and benefits of this invention will be apparent to those of ordinary skill in the art having reference to the following drawings and description herein.